John VanNewkirk
Customer Use Case
Originally published January 22, 2025. Updated August 12, 2026.
In this CheckSum customer application, a leading European automotive electronics manufacturer reduced untested work in process (WIP) by 99%, lowered production-test costs by 31%, and increased test output to 25% above the output of its surface-mount technology (SMT) line. The manufacturer achieved those results by replacing a sequential capacity constraint with parallel in-circuit test, device programming, and functional test for panelized printed circuit board assemblies (PCBAs).
The short answer: Higher-density panels multiplied the number of PCBAs produced during each SMT cycle, but the existing test process did not scale at the same rate. Parallel PCBA testing allowed multiple boards to be tested and programmed simultaneously, bringing test throughput back in line with production demand.
The Challenge: Untested WIP Was Growing Behind a High-Speed SMT Line
The manufacturer operated high-volume SMT lines for automotive electronics. Its smaller products were built in multi-up panels and represented a large, growing share of production. Despite the speed of the assembly operation, these products carried higher costs and greater quality risk than the company's larger assemblies.
The problem appeared after assembly. SMT output overwhelmed the PCBA production-test process, creating racks of untested panels. When a manufacturing defect was finally detected, thousands of PCBAs could already have passed through the line. That delay increased the exposure to sorting, rework, and scrap.
Why Panel Density Increased SMT Output Faster Than Test Capacity
For this manufacturer, the SMT line could process an 8-up panel in about the same panel cycle as a 2-up panel. The output measured in individual PCBAs increased substantially, but testing the eight smaller boards took up to three times longer than testing the two-board panel.
That difference occurred because assembly and test scale in different ways. SMT equipment processes one panel while placing the required components. Conventional test often repeats board-level operations for each device under test (DUT). As the panel changed from 4-up to 8-up and the factory installed faster pick-and-place equipment, the downstream mismatch became more severe.
| Production stage | What changed as panel density increased | Capacity effect |
|---|---|---|
| SMT assembly | More individual PCBAs were produced during each panel cycle | Board output increased without a proportional increase in panel cycle time |
| Sequential ICT, programming, and functional test | Board-level operations were repeated for each DUT | Test throughput fell behind SMT output and WIP accumulated |
| Parallel PCBA test | Multiple DUTs were processed during the same test cycle | Test capacity could match or exceed the required SMT takt time |
Test and programming time also depended on the actual application: test coverage, instrument settling, memory size, device speed, communication bus, functional dwell time, and fixture or handling steps. A faster SMT line therefore could not be balanced by changing one generic test-time setting.
Why Approved Equipment Did Not Eliminate the Bottleneck
The manufacturer's corporate group maintained an approved vendor list (AVL) for factory equipment. The plants used approved systems for in-circuit test (ICT), onboard programming, and functional test. Those standards supported consistency, but they did not change the underlying capacity architecture: too much of the test flow still processed boards sequentially.
The lesson is broader than any one equipment list. Selecting capable individual systems does not guarantee a balanced line. Capacity must be evaluated across the complete PCBA production-test flow and compared with the required panel takt time.
The Goal: Match PCBA Production Test to SMT Takt Time
The manufacturer established four priorities for its 8-up to 12-up products:
- Eliminate the buildup of untested WIP.
- Reduce production-test cost.
- Reduce rework and scrap through faster process feedback.
Increase test throughput enough to keep pace with the SMT line.
The Solution: Parallelize ICT, Programming, and Functional Test
The practical response was to process more than one board at a time. CheckSum's parallel PCBA testing architecture can apply parallelism to the major parts of the test flow:
- Multi-Core in-circuit test (ICT) runs eligible test content on multiple PCBAs during the same cycle.
- MultiWriter in-system programming (ISP), also called onboard programming, programs multiple devices and DUTs in parallel.
- Parallel Functional Test (PFT) executes eligible board-level functional tests across multiple PCBAs or a full panel simultaneously.
- Automated inline or off-line handling can be configured around the application, production target, and required test sequence.
The correct degree of parallelism can differ by process. ICT, ISP, and functional test do not necessarily need the same number of simultaneous DUTs. What matters is the cycle time of the complete test cell and whether it satisfies the required SMT takt time with the necessary coverage.
CheckSum platforms such as the ILS-X2 dual-panel automated test system and 12KN off-line test system support combinations of ICT, programming, and functional test. Where the production flow requires automated inline ICT, an ILS-X2 configuration can integrate those test disciplines with automated panel handling; the 12KN supports them in an off-line format. The final configuration should be based on the board, panel, production environment, and test requirements.
The Results: 99% Less WIP and 31% Lower Cost
After CheckSum's parallel test solution was implemented, the customer reported:
- 99% reduction in untested WIP
- 31% reduction in production-test costs
- Test output 25% greater than SMT output
- A major reduction in rework and scrap
- Faster feedback to the SMT process
- Less equipment, labor, and floor-space pressure than a proportional expansion of sequential test capacity would have required
Testing 8 to 10 boards simultaneously eliminated the large WIP accumulation and restored near-real-time process feedback. With test output operating above SMT output, the test area could absorb normal production variation instead of allowing panels to wait in inventory. The manufacturer also recovered valuable factory floor space after the WIP racks were cleared.
What Manufacturers Can Learn From This Case
This case shows why test capacity should be evaluated whenever panel density or SMT capacity changes. A project that was balanced at 4-up may become constrained at 8-up. A faster placement machine can also move the bottleneck downstream even if the test program itself has not changed.
The capacity review should include:
- Boards per panel and expected panel mix
- Required panel takt time and production volume
- ICT coverage and measurement sequence
- ISP file sizes, device limits, interfaces, and programming time
- Functional-test steps, communications, and dwell time
- Fixture actuation, conveyance, loading, unloading, and data-handling time
- Single-panel, dual-panel, sequential, and simultaneous operating options
The best answer is not automatically the most parallel configuration. It is the architecture that meets the production target with appropriate coverage, reliability, maintainability, and cost.
Compare Your PCBA Test Capacity With Your SMT Line
If untested panels are accumulating - or if new panelization and SMT upgrades are likely to increase output - compare the complete test cycle with the real line requirement before adding more sequential capacity.
CheckSum's Free Project Analysis reviews the application, including ICT, programming, functional test, handling, takt time, recommended system configuration, and budgetary requirements.
Request a Free Project Analysis to determine where parallel PCBA testing can improve throughput, WIP, and cost in your production process.
