Boundary-scan (also called “JTAG Test” after the Joint Test Action Group which developed the technique in the late 1980s) provides a means to test interconnects between integrated circuits on a circuit board “virtually” without using physical test probes.

Despite its promise to reduce testing cost, the added cost of designing boundary-scan circuitry into semiconductor devices has hindered its widespread adoption for a number of years. 

However, the increasing density of boards and fine pitch components such as BGAs has significantly diminished the physical accessibility required for in-circuit test.  As a result, boundary-scan is growing in popularity as it counteracts the loss of electrical access, increasing fault coverage on the small and very dense boards that are a feature of handheld products such as phone handsets and portable entertainment electronics. 

While there are some boundary-scan circuit designs that can effectively eliminate the requirement for in-circuit test, the vast majority of boards still require in-circuit testing, with boundary-scan acting as a vital tool to increase overall fault coverage of the board.  In one case, boundary-scan resulted in a 30% increase of fault coverage.

The major advantage of boundary-scan is that no knowledge of actual device function is required to perform thorough interconnect testing.  Boundary-scan eliminates the cost and time required to develop and debug traditional digital vector test routines such as those required for ‘backdrive’ in-circuit test.

Theory of Operation

The IEEE 1149.1 standard specifies the method, hardware and software parameters required to test interconnects among scan devices mounted on a printed circuit board (often called Boundary In-Circuit Test).

To comply with the IEEE 1149.1 standard a boundary-scan chip requires:

• Boundary-scan cells at each pin of the device.  Each cell is basically a multiplexer and latch. The boundary-scan cell is shown as a small box at each pin in the diagram at right.
• In ‘boundary-scan mode’ the latches at each pin are connected serially in a “scan path” (also called a “scan chain”) such that a data pattern is shifted into the latch at each pin via the “TDI” (Test Data In) pin.
• Captured test data is serially shifted out via the “TDO” (Test Data Out) pin where it is read by the tester and compared to the expected results.
• The Test Access Port (TAP) controller provides the necessary logic to switch the device into and out of ‘boundary-scan mode’ and control the overall test sequence.
• Three control lines (TMS, TCK, TRST) perform these required functions in boundary test mode

The second half of the boundary-scan equation is the software required to:

• Generate the appropriate serial data pattern to be shifted into the boundary-scan cells at the TDI pin of the device.
• Interpret the data output of each device such that anomalous results can be translated to a clear description of the type and location of the fault, e.g., an open on net X or a short between net Y and net Z.

Most available boundary-scan tools provide rigorous algorithms to stimulate and detect faults and to isolate faults to specific nets, devices, and pin numbers.  The majority of these tools employ the Boundary-scan Description Language (BSDL).  BDSL specifications were added to the IEEE 1149.1 standard in 1994.

A variety of boundary-scan tool vendors supply boundary-scan stimulus/measurement software and hardware adaptor tools, which can be added to any CheckSum Analyst system.